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| FEDS5424331-01 1 Semiconductor MSM5424331 222,720-Word x 24-Bit Field Memory This version: Sep. 2000 GENERAL DESCRIPTION The MSM5424331 is an image data processing field memory organized as 222,720 (768 pixels by 290 lines) by 24 bits that can switch between the FIFO mode where the MSM5424331 is used as an ordinary field memory and a block access mode where the MSM5424331 can easily exchange data with personal computer and the like. Serial writing in and serial reading from the MSM5424331 are performed line by line. In the FIFO mode, any line can be selected by specifying their addresses by the Serial Address input. In the Block Access mode, any line or word address (10 bits) can be set by entering the address through the address multiplexer. As the MSM5424331 in the Block Access mode can be controlled by RAS and CAS signals, it can easily interface to the MPU. The MSM5424331 contains dynamic memory cells. In the FIFO mode, the memory cells are automatically refreshed by the self refresh control circuit, but in the Block Access mode, the memory cells must be refreshed by the CAS before RAS Refresh function. The MSM5424331 is not designed for high end use in such applications as medical systems, professional graphics systems which require long term picture storage, data storage systems and others. 1/34 FEDS5424331-01 1 Semiconductor MSM5424331 FEATURES * Switching between FIFO and Block Access modes by the D/F pin FIFO mode: Serial write/read operation by line-by-line accessing Block Access mode: Fast write/read operation on an 8-word basis by the RAS and CAS control * Organization of 768 x 290 x 24 bits FIFO mode: Input x 12 or x 24 controlled by L/UWE Output x 24 Block Access mode: Input x 12 (Two 768 x 290 x 12-bit banks are controlled by L/UWE.) Output x 12 (Two 768 x 290 x 12-bit banks are controlled by A9.) * Asynchronous operation Input and output asynchronous operation enabled only in the FIFO mode Single write or read operation in the Block Access mode * Serial Read and Write Cycle times (in both the FIFO mode and the Block Access mode) Cycle time: 60 ns Access time: 50 ns * Operating supply voltage: 2.8 to 3.3 V * Refresh FIFO mode: Self refresh Block Access mode: by the CAS before RAS refresh function (290 cycles/8 ms) * Address input FIFO mode: Setting random line address by the serial address input Block Access mode: Setting random address in the address multiplexer by the RAS and CAS control * Selectable serial address input setting or various address resetting in the FIFO mode * Package: 70-pin 400 mil plastic TSOP (Type 2) (TSOP(2)70-P-400-0.50-K) (Product: MSM5424331TS-AK) 2/34 FEDS5424331-01 1 Semiconductor MSM5424331 PIN CONFIGURATION (TOP VIEW) RADE/RX 1 RCLK 2 RE DO0[DQ0] DO1[DQ1] DO2[DQ2] DO3[DQ3] DO4[DQ4] DO5[DQ5] VSS DO6[DQ6] DO7[DQ7] DO8[DQ8] DO9[DQ9] DO10[DQ10] DO11[DQ11] VCC VCC DO12 DO13 DO14 DO15 DO16 DO17 VCC DO18 DO19 DO20 DO21 DO22 DO23 WXINC WR/TR WADE/RX WXAD 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 RXAD 69 RR 68 RXINC 67 VSS 66 D/F 65 DIN0[RAS] 64 DIN1[CAS] 63 DIN2[A0] 62 DIN3[A1] 61 DIN4[A2] 60 DIN5[A3] 59 DIN6[A4] 58 DIN7[A5] 57 DIN8[A6] 56 DIN9[A7] 55 DIN10[A8] 54 DIN11[A9] 53 WAIT 52 VSS 51 DIN12 50 DIN13 49 DIN14 48 DIN15 47 DIN16 46 DIN17 45 DIN18 44 DIN19 43 DIN20 42 DIN21 41 DIN22 40 DIN23 39 WCLK 38 LWE 37 UWE 36 IE 70-Pin Plastic TSOP (2) (K Type) 3/34 FEDS5424331-01 1 Semiconductor MSM5424331 Pin Name FIFO Mode Block Mode RCLK RE DO0 - 11 DO12 - 23 RR RXINC RADE/RX RXAD WCLK LWE UWE IE DIN0 DIN1 DIN2 - 11 DIN12 - 23 WR/TR WXINC WADE/RX WXAD WAIT D/F VCC VSS D/F RAS CAS A0 - A9 LWE UWE RE DQ0 - 11 FIFO Mode Address Setting Cycle Read X Serial Address Strobe -- -- -- Read Address Reset Mode Enable Read X Address Increment Read X Address Input Enable Read X Address Reset Read X Serial Address Data Write X Serial Address Strobe -- -- -- -- -- -- -- Write Address Reset Mode Enable Write X Address Increment Write X Address Input Enable Write X Address Reset Write X Serial Address Data -- Mode Change (D/F = L) Power Supply Voltage (3.0 V) Ground (0 V) Serial Read/Write Cycle Serial Read Clock Read Enable Data Output Data Output -- -- -- -- Serial Write Clock Write Enable Write Enable Input Enable Data Input Data Input Data Input Data Input Write Data Transfer -- -- -- -- Block Mode -- Read Enable Data Input/Output -- -- -- -- -- -- Write Enable Write Enable -- X Address Strobe Y Address Strobe Address Input -- -- -- -- -- External Synchronous Signal Mode Change (D/F = H) Note: Same power supply voltage level must be provided to every VCC pin. Same ground voltage level must be provided to every VSS pin. 4/34 FEDS5424331-01 1 Semiconductor MSM5424331 BLOCK DIAGRAM DQ0-11 DOUT12-23 12 DQ0-11 DIN0-11 DOUT0-11 12 DIN12-23 UWE IE IE LWE RE 12 12 DOUT Buffer 12 Write Buffer Write Buffer 12 DOUT Buffer Read Register U-Bank Memory Cell Array (760 x 290 x 12) Write Register Write Register L-Bank Memory Cell Array (760 x 290 x 12) X-Decoder X-Decoder Memory Controller Read Register WAIT VBB Generator FIFO Mode Control BLOCK Mode Control Refresh Control RAS CAS LWE UWE D/F Mode Control WCLK WR/TR WADE/RX WXAD WXINC RCLK RR RADE/RX RXAD RXINC A0-A9 RAS CAS RE 5/34 FEDS5424331-01 1 Semiconductor MSM5424331 PIN FUNCTION Read Related D/F This signal switches between the FIFO mode and the Block Access mode. The FIFO mode is selected when this signal is low "L" and the Block Access mode is selected when this signal is high "H". RCLK: Read Clock RCLK is the read control clock input in the FIFO mode. Synchronized with RCLK's rising edge, serial read access from read ports is executed when RE is low. The internal counter for the serial read address is incremented automatically on the rising edge of RCLK. In a read address set cycle, all the read address bits which were input from RXAD pin are stored into internal address registers synchronized with RCLK. In this address set cycle, RADE/RX must be held high and RR must be held low. In the read address reset cycle, various read address reset modes can be set synchronously with RCLK. These reset cycles work to replace complicated serial address control which requires many RCLK clocks with a simple reset cycle control requiring only a single RCLK cycle. It greatly facilitates memory access. In the Block Access mode, the RCLK signal is ignored. RE: Read Enable RE is a read enable clock input in the FIFO mode. RE enables or disables both internal read address pointers and data-out buffers. When RE is low, the internal read address pointer is incremented synchronously with RCLK. When RE is high, even if the RCLK is input, the internal read address pointer is not incremented. The output pins are enabled in the read cycle of the Block Access mode when this pin (RE) is low "L". RR: Read Reset RR is a read reset control input in the FIFO mode. Read address reset modes are defined when RR level is high according to the "FUNCTION TABLE for read". In the Block Access mode, the RR signal is ignored. RXINC: Read X Address Increment RXINC is a read X address (or line address) increment control input in the FIFO mode. In the read address reset cycle, defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high with RADE/RX low. In the Block Access mode, the RXINC signal is ignored. RADE/RX: Read Address Enable/Read X Address Reset Logic Function RADE/RX is a dual function control input in the FIFO mode. RADE, one of the two functions of RADE/RX, is a read address enable input. In the read address set cycle, X address (or line address) input from the RXAD pin is latched into internal read X address register synchronously with RCLK. RX, the second function of RADE/RX, works as an element to set read X address (or line address) reset mode. In an address reset mode cycle, defined by RR high, read X address is set to 0 when RADE/RX is pulled high with RXINC low. In the Block Access mode, the RADE/RX signal is ignored. 6/34 FEDS5424331-01 1 Semiconductor MSM5424331 RXAD: Read X Address RXAD is a read X address (or line address) input in the FIFO mode. RXAD specifies the line address. 10 bits of read X address data are input serially from RXAD. The bits of an address are fetched starting from the higher order bits. The most significant bit (A9) is ignored. In the Block Access mode, the RXAD signal is ignored. DO0-11 (DQ0-11), DO12-23: Data-Outs In the FIFO mode, these pins are used as serial outputs. In the Block Access mode, pins DO0 to DO11 (DQ0 to DQ11) are used as input and output pins. 7/34 FEDS5424331-01 1 Semiconductor MSM5424331 Write Related WCLK: Write Clock WCLK is a write control clock input in the FIFO mode. Synchronized with WCLK's rising edge, serial write access into write ports is executed when LWE or UWE is low. According to WCLK clocks, the internal counter for the serial address is incremented automatically. In a write address set cycle, all the write addresses which were input from WXAD are stored into internal address registers synchronously with WCLK. In this address set cycle, WADE/RX must be held high and WR/TR must be held low. In the write address reset cycle, various write address reset modes can be set synchronously with WCLK. These reset cycles replace complicated serial address control with simple reset cycle control which requires only one WCLK cycle. It greatly facilitates memory access. In the Block Access mode, the WCLK signal is ignored. LWE: Write Enable LWE is a write enable clock input in the FIFO mode. LWE enables or disables both internal write address pointers and data-in buffers. When LWE is low, the internal write address pointer is incremented synchronously with WCLK. When LWE is high, even if WCLK is input, the internal write address pointer is not incremented. In the Block Access mode, writing in the L-bank is performed when LWE goes low at the falling edge of DIN0 (RAS). UWE: Write Enable UWE is a write enable clock input in the FIFO mode. UWE enables or disables both internal write address pointers and data-in buffers. When UWE is low, the internal write address pointer is incremented synchronously with WCLK. When UWE is high, even if WCLK is input, the internal write address pointer is not incremented. In the Block Access mode, writing in the U-bank is performed when UWE goes low at the falling edge of DIN0 (RAS). DIN0 (RAS): Data-In DIN0 is serial data-in in the FIFO mode. In the Block Access mode, this pin serves as RAS. On the falling edge of this signal, the 10-bit row address (A0 to A9) is fetched. DIN1 (CAS): Data-In DIN1 is serial data-in in the FIFO mode. In the Block Access mode, this pin serves as CAS. On the falling edge of this signal, the 10-bit column address (A0 to A9) is fetched. This column address becomes a start address in the Block Access mode. When DIN1 (CAS) is toggled while DIN0 (RAS) remains low, the read/write operation in the Block Access mode is enabled. DIN2-11 (A0-A9): Data-Ins DIN2-11 are serial data-ins in the FIFO mode. In the Block Access mode, these pins serve as a row or column address input (A0 to A9). These pins fetch a row address when DIN0 (RAS) is active or a column address when DIN1 (CAS) is active. DIN12-23: Data-Ins DIN12-23 are serial data-ins in the FIFO mode. 8/34 FEDS5424331-01 1 Semiconductor MSM5424331 WR/TR: Write Reset/Write Transfer WR/TR is a write reset control input in the FIFO mode. Write address reset modes are defined when WR/TR level is high according to the "FUNCTION TABLE for write". When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the written data in the write register to corresponding memory cells. In the Block Access mode, the WR/TR signal is ignored. WXINC: Write X Address Increment WXINC is a write X address (or line address) increment control input in the FIFO mode. In the write address reset cycle, defined by WR/TR high, the write X address (or line address) is incremented by 1 when WXINC is pulled high with WADE/RX low. In the Block Access mode, the WXINC signal is ignored. WADE/RX: Write Address Enable/Write X Address Reset Logic Function WADE/RX is a dual functional control input in the FIFO mode. WADE, one of the two functions of WADE/RX, is a write address enable input. In the write address set cycle, X address (or line address) input from the WXAD pin is latched into internal write X address register synchronously with WCLK. RX, the second function of WADE/RX, works as an element to set write X address (or line address) reset mode. In the write address reset cycle, defined by WR/TR high, the write X address is set to 0 when WADE/RX is pulled high with WXINC low. In the Block Access mode, the WADE/RX signal is ignored. WXAD: Write X Address WXAD is a write X address (or line address) input in the FIFO mode. WXAD specifies line address. 10 bits (0 to 9) of write X address data are input serially from WXAD. The bits of an address is fetched starting from the higher order bits. The most significant bit (A9) is ignored. In the Block Access mode, the WXAD signal is ignored. IE: Input Enable IE is an input enable in the FIFO mode which controls the write operation. When IE is high, the input operation is enabled. When IE is low, the write operation is masked. When LWE and UWE signals are low, and IE low, the internal serial write address pointer is incremented on the rising edge of WCLK without actual write operations. This function facilitates picture in picture function in a TV system. In the Block Access mode, the IE signal is ignored. WAIT: This output pin enables interface to the MPU in the Block Access mode. To cause the MSM5424331 to operate in the Block Access mode, set the D/F pin high and afterward set RAS low. The output of the WAIT pin goes low while a row or column address is set. Perform the actual read or write operation in the Block Access mode after the output of the WAIT pin goes high again. 9/34 FEDS5424331-01 1 Semiconductor MSM5424331 OPERATION MODE FIFO Mode The FIFO mode is set when the D/F pin is set low. 1. Write 1.1 Write operation Before the write operation begins, X address (or line address) must be input to set the initial bit address for the following serial write access. When LWE or UWE is low, a set of serial write data on DIN0-11 or DIN1223 is written into write registers attached to the DRAM memory arrays temporarily on the rising edge of WCLK. The LWE pin controls the write operation of DIN0 to DIN11 (12 bits) and the UWE pin controls the write operation of DIN12 to DIN23 (12 bits). Following 24-bit-width serial input data is written into the memory locations in the write register designated by an internal write address pointer which is advanced by WCLK. This enables continuous serial write on a line. When write clock WCLK and read clock RCLK are tied together and are controlled by a common clock or CLK, more than two MSM5424331 can be cascaded directly without any delay devices between the MSM5424331 because the read timing is delayed by one CLK cycle to the write timing. When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order to store the written data in the write registers to the corresponding memory cells in the DRAM memory arrays. 1.2 Write address pointer increment operation The write address pointer is incremented synchronously with WCLK when LWE or UWE is low. Relationship between the LWE, UWE, and IE input levels, Write Address pointer, and data input status WCLK Rise LWE L L H L L H H UWE L H L L H L H IE H H H L L L -- Internal Write Address Pointer Increments both L- and U-banks. Increments the L-bank only. Increments the U-bank only. Increments both L- and U-banks. Increments the L-bank only. Increments the U-bank only. Stopped Not Inputted Inputted Data Input When LWE or UWE is low and IE is high, the write operation is enabled. If IE level goes low while WCLK is active, the write operation is halted but the write address pointer will continue to advance. That is, IE enables a write mask function. When LWE or UWE goes high, the write address pointer stops without WCLK. 10/34 FEDS5424331-01 1 Semiconductor MSM5424331 2. Read 2.1 Read operation Before the read operation begins, the X address (or line address) must be input for setting initial bit address for the following serial read access. When RE is low, a set of serial 24-bit-width read data on DO0-11, DO12-23 pins is read from read registers attached to DRAM memory arrays on the rising edge of RCLK. Each access time is specified by the rising edges of RCLK. 2.2 Read address pointer increment operation The read address pointer is incremented synchronized with RCLK when RE level is low. The output data will be undefined when the read address pointer is incremented above the last address of one line. 3. Initial Address Setting (Write/Read Independent) Any read operations are prohibited in the read initial address set period. Similarly, any write operations are prohibited in the write initial address set period. Note that read initial address set and write initial address set can occur independently. Similarly, read access can be achieved independently from write initial address set period and write access can be achieved independently from read initial address set cycles. 3.1 Write address setting WADE/RX enables initial read address inputs. When WADE/RX is high, 10 bits of serial X address (or line address) are input from higher order bits from WXAD. The operations above enable selection of specific lines randomly and enables the start of serial write access synchronized with write clock WCLK. Address for each line must be input between each line access. In other words, MSM5424331's write is achieved in a "line by line" manner. Any write operations are prohibited in the initial write address set periods. Serial write input enable time tSWE must be kept for starting a serial write just after the initial write address set period. The most significant bit (A9) is ignored. 3.2 Read address setting RADE/RX enables initial read address inputs. When RADE/RX is high, 10 bits of serial X address (or line address) are input from higher order bits from RXAD. The operations above enable selection of specific lines randomly and enables the start of serial read access synchronized with read clocks, RCLK. Address for each line must be input between each line access. In other words, MSM5424331's read operation is achieved in "line by line" manner. Any read operations are prohibited in the initial read address set periods. Serial read operations are prohibited while RADE/RX is high. Serial read port enable time tSRE must be kept for starting a serial read just after the initial read address set period. The most significant bit (A9) is ignored. 11/34 FEDS5424331-01 1 Semiconductor MSM5424331 4. Initial Address Reset Modes (Write/Read Independent) The initial address reset modes replace complicated read or write initial address settings with simple reset cycles. Initial address reset modes are selected by RR high during read and WR/TR high during write. As in normal read or write address settings, any read operations are prohibited in the read address reset cycles. Similarly, any write operations are prohibited in the initial write address reset cycles. Note that read initial address reset and write initial address reset can occur independently. Similarly, read access can be achieved independently from write initial address reset cycles and write access can be achieved independently from read initial address reset cycles. Input addresses are stored into address registers which are connected with address counter which controls address pointer operation. In the serial access operation, the input address into the address registers are kept. Serial write data input enable time tSWE and serial read port read enable time tSRE must be kept for starting serial read or write just after the initial read or write address reset cycles. Refer to the "FUNCTION TABLE" shown later. 4.1 Line hold operation (read only) By the "Line hold operation" logic which is composed by a combination of control inputs' level, access is executed starting from the first word on the current line. 4.2 Original address reset operation By the "Original address reset" logic, the address counter is set to (0,0). After the reset mode, serial access starts from the address (0,0) . The address counter is reset by this reset mode but the address register, which stored input address in the previous address reset cycle or address set cycle, is not reset. The non-initialized address can be used as a preset address in "address jump reset" mode. 4.3 Line increment operation By the "Line increment operation" logic, the X address counter is incremented by one from the current X address. That is, serial access from the Y = (0) on the next line is enabled. 4.4 Address jump operation By the "Address jump operation" logic, a jump may be caused to the initialized line address. Note: During one reset setting cycle, a plurality of resets cannot be set. 12/34 FEDS5424331-01 1 Semiconductor MSM5424331 Block Access Mode The Block Access mode is configured when the D/F pin is set high. 1. Write Operation The MSM5424331 fetches a 10-bit row address form lines A0 to A9 at the falling edge of the DIN0 (RAS) pin and a 10-bit column address (10 bits long) from the lines at the falling edge of the DIN1 (CAS) pin. With this operation, a head address can be set arbitrarily. For a write operation, the LWE or UWE pin must be set low at the falling edge of DIN0 (RAS). The actual fetching of write data is performed at the falling edge of DIN1 (CAS) after tCASB. The write data is entered from I/O pins DQ0 to DQ11. The write data is written in the L-bank at the falling edge of DIN0 (RAS) when LWE is low and UWE is high or in the U-bank when LWE is high and UWE is low. When both LWE and UWE are both low, data is written in either the L- or U-bank (which is undefined). Data storage in the memory cell is executed at the rising edge of DIN0 (RAS) after the block write operation is completed. When changing a write operation in the FIFO mode to a write operation in the Block Access mode, it is required to monitor on the WAIT pin whether self refresh in the FIFO mode is completed. Perform the block write operation after the output of the WAIT pin is high. The block read operation and FIFO operation are disabled during a block write operation. Read Operation The MSM5424331 fetches a 10-bit row address from lines A0 to A9 at the falling edge of the DIN0 (RAS) pin and a 10-bit column address from the lines at the falling edge of the DIN1 (CAS) pin. With this operation, a head address can be set randomly. For a read operation, the LWE or UWE pin must be set high at the falling edge of DIN0 (RAS). Read data is fetches at the falling edge of DIN1 (CAS) after tCASB. The RE pin should be set low at the falling edge of DIN1 (CAS). The read data is output from DQ0 to DQ11 I/O pins. The L- or U-bank from which data is read is selected by the status of the "A9" bit of the row address. Data is read from the L-bank when the "A9" bit is "0" or from the U-bank when the "A9" bit is "1". When changing a read operation in the FIFO mode to a read operation in the Block Access mode, it is required to monitor on the WAIT pin whether self refresh in the FIFO mode is completed. Perform the block read operation after the output of the WAIT pin is high. The block write operation and FIFO operation are disabled during a block read operation. 2. Refresh 1. FIFO Mode In the FIFO mode, the MSM5424331 performs self refresh. Block Access Mode In the Block Access mode, self refresh is disabled. Use the CAS before RAS refresh function to refresh. Addressing from A0 to A9 pins is not required because refresh addresses are automatically given by the built-in refresh counter. 2. 13/34 FEDS5424331-01 1 Semiconductor MSM5424331 Power On Power must be applied to RCLK, WCLK, and IE input signals to pull them "Low", and to RE, LWE, UWE, DIN0 (RAS), and DIN1 (CAS) input signals to pull them "High" before or when the VCC supply is turned on. After power-up, the device is designed to begin proper operation in at least 200 s after VCC has reached the specified voltage (2.8 V). After 200 s, a minimum of one line dummy write operation and read operation is required according to the address setting mode, because the read and write address pointers are not valid after power-up. After that, an operation can be started in the FIFO or Block Access mode. New Data Read Access in the FIFO Mode In order to read out "new data", the delay between the beginning of a write address setting cycle and read address setting cycle must be at least two lines. Old Data Read Access in the FIFO Mode In order to read out "old data", the delay between the beginning of a write address setting cycle and read address setting cycle must be more than 0 but less than a half line. 14/34 FEDS5424331-01 1 Semiconductor MSM5424331 FUNCTION TABLE 1. Write (D/F = "L") Mode Write Transfer No. 1 2 Address Reset Mode 3 4 Address Setting Mode 5 Description of Operation Write Transfer Reset Line Increment Address Jump First Address Setting WR/TR WXINC WADE/RX H H H H L L L H H L L H L H H X address cleared to (0, 0) X address Increment to (Xn + 1, 0) X address jump to (Xi, 0) X address set Internal Address Pointer Note: For write, Line hold is not provided. 2. Read (D/F = "L") Mode No 1 2 Description of Operation Line Hold Reset Line Increment Address Jump First Address Setting RR H H H H L RXINC L L H H L RADE/RX L H L H H Internal Address Pointer X address hold to (Xn, 0) X address cleared to (0, 0) X address increment to (Xn + 1, 0) X address jump to (Xi, 0) X address set Address Reset Mode 3 4 Address Setting Mode 5 15/34 FEDS5424331-01 1 Semiconductor MSM5424331 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Pin Voltage Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT lOS PD Topr Tstg Condition Ta = 25C, with respect to VSS Ta = 25C Ta = 25C -- -- Rating -0.5 to 4.2 V 50 mA 1W 0 to 70C -55 to 150C Recommended Operating Conditions (Ta = 0 to 70C) Parameter Power Supply Voltage Power Supply Voltage "H" Input Voltage "L" Input Voltage Symbol VCC VSS VIH VIL Min. 2.8 0 2.1 -0.5 Typ. 3.0 0 VCC 0 Max. 3.3 0 VCC + 0.3 0.8 Unit V V V V DC Characteristics (VCC = 2.8 to 3.3 V, Ta = 0 to 70C) Parameter "H" Output Voltage "L" Output Voltage Input Leakage Current Output Leakage Current Power Supply Current (During Operation) Power Supply Current (During Standby) Symbol VOH VOL ILI ILO ICC1 ICC2 Condition lOH = -0.1 mA lOL = 0.1 mA 0 < VI < VCC Other input voltage 0 V 0 < VO < VCC 60 ns cycle Input pin = VIL/VIH Min. 2.2 -- -10 -10 -- -- Max. -- 0.6 10 10 90 5 Unit V V A A mA mA Capacitance (Ta = 25C, f = 1 MHz) Parameter Input Capacitance Output Capacitance Symbol CI CO Max. 7 7 Unit pF pF 16/34 FEDS5424331-01 1 Semiconductor MSM5424331 AC Characteristics (1/3) FIFO Mode Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70C) Parameter WCLK Cycle Time WCLK "H" Pulse Width WCLK "L" Pulse Width Serial Write Address Input Active Set-up Time Serial Write Address Input Active Hold Time Serial Write Address Input Inactive Hold Time Serial Write Address Input Inactive Set-up Time Write Transfer Instruction Set-up Time Write Transfer Instruction Hold Time Write Transfer Instruction Inactive Hold Time Write Transfer Instruction Inactive Set-up Time Serial Write X Address Set-up Time Serial Write X Address Hold Time Serial Write Data Input Enable Time Write Instruction Set-up Time Write Instruction Hold Time Write Instruction Inactive Hold Time Write Instruction Inactive Set-up Time Input Data Set-up Time Input Data Hold Time WR/TR-WCLK Active Set-up Time WR/TR-WCLK Active Hold Time WR/TR-WCLK Inactive Hold Time WR/TR-WCLK Inactive Set-up Time WXINC-WCLK Active Set-up Time WXINC-WCLK Active Hold Time WXINC-WCLK Inactive Hold Time WXINC-WCLK Inactive Set-up Time WADE/RX-WCLK Active Set-up Time WADE/RX-WCLK Active Hold Time WADE/RX-WCLK Inactive Hold Time WADE/RX-WCLK Inactive Set-up Time IE Enable Set-up Time IE Enable Hold Time IE Disable Set-up Time IE Disable Hold Time Symbol tWCLK tWWCLH tWWCLL tWAS tWAH tWADH tWADS tWTRS tWTRH tWTDH tWTDS tWXAS tWXAH tSWE tWES tWEH tWEDH tWEDS tDS tDH tWRS tWRH tWRDH tWRDS tWINS tWlNH tWINDH tWINDS tWRXS tWRXH tWRXDH tWRXDS tIES tIEH tIEDS tIEDH Min. 60 28 28 5 7 7 7 5 7 7 7 5 7 1500 5 7 7 7 5 12 5 7 7 7 5 7 7 7 5 7 7 7 5 7 7 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17/34 FEDS5424331-01 1 Semiconductor MSM5424331 AC Characteristics (2/3) FIFO Mode Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70C) Parameter RCLK Cycle Time RCLK "H" Pulse Width RCLK "L" Pulse Width Serial Read Address Input Active Set-up Time Serial Read Address Input Active Hold Time Serial Read Address Input Inactive Hold Time Serial Read Address Input Inactive Set-up Time Serial Read X Address Set-up Time Serial Read X Address Hold Time RE Enable Set-up Time RE Enable Hold Time RE Disable Hold Time RE Disable Set-up Time Read Port Read Enable Time Read Port Read Data Hold Time Access Time from RCLK Read Data Hold Time from RE RR-RCLK Active Set-up Time RR-RCLK Active Hold Time RR-RCLK Inactive Hold Time RR-RCLK Inactive Set-up Time RXINC-RCLK Active Set-up Time RXINC-RCLK Active Hold Time RXINC-RCLK Inactive Hold Time RXINC-RCLK Inactive Set-up Time RADE/RX-RCLK Active Set-up Time RADE/RX-RCLK Active Hold Time RADE/RX-RCLK Inactive Set-up Time RADE/RX-RCLK Inactive Hold Time BLOCK-FRAM Mode Change Set-up Time BLOCK-FRAM Mode Change Hold Time Transition Time (Rise and Fall) Symbol tRCLK tWRCLH tWRCLL tRAS tRAH tRADH tRADS tRXAS tRXAH tRES tREH tREDH tREDS tSRE tOH tAC tDDRE tRRS tRRH tRRDH tRRDS tRINS tRINH tRINDH tRINDS tRRXS tRRXH tRRXDS tRRXDH tDFS tDFH tT Min. 60 28 28 5 7 7 7 5 7 5 tAC 7 7 1500 12 -- 12 5 7 7 7 5 7 7 7 5 7 7 7 20 5 2 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18/34 FEDS5424331-01 1 Semiconductor MSM5424331 AC Characteristics (3/3) Block Mode Measurement Conditions: (VCC = 2.8 to 3.3 V, Ta = 0 to 70C) Parameter D/F to RAS Precharge Time D/F to CAS Precharge Time BLOCK Mode Set-up Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time CAS to RAS Precharge Time CAS Pulse Width CAS Precharge Time BLOCK Mode Start to CAS Pulse Width BLOCK Mode Cycle Time RAS Precharge Time (WRITE) RAS Precharge Time (READ) Access Time from RAS Access Time from CAS Data-in Set-up Time Data-in Hold Time Data-in Hold Time (Head Bit) BLOCK Mode Write Hold Time BLOCK Mode Read Hold Time Write Command Set-up Time Write Command Hold Time Read Command Set-up Time Read Command Hold Time RAS Hold Time Output Data Hold Time from RE Output Data Enable Time from RE Output Buffer Turn-off Delay Time Read Data Hold Time from CAS Write Command Set-up Time from CAS Write Command Hold Time from CAS RAS Precharge to CAS Active Time (CAS before RAS) RAS Pulse Width (CAS before RAS) CAS before RAS Cycle Time (CAS before RAS) RAS Precharge Time (CAS before RAS) CAS Set-up Time (CAS before RAS) CAS Hold Time (CAS before RAS) CAS Precharge Time (CAS before RAS) Transition Time (Rise and Fall) Symbol tDRP tDCP tBS tASR tAHR tASC tAHC tRCD tCRP tCAS tCP tCASB tBC tRPW tRPR tRAC tBAC tBDS tBDH tFBDH tBWH tBRH tWCS tWCH tRCS tRCH tRSH tDDRE tDERE tOFF tBOH tCWCS tCWCH tRPC tRASB tRC tRP tCSR tCHR tCPN tT Min. 60 60 40000 0 10 0 15 20 10 28 28 600 60 400 60 -- -- 0 15 585 15 15 0 15 0 15 50 12 -- 12 15 0 15 10 400 465 61 10 15 28 2 Max. -- -- -- -- -- -- -- 35 -- -- -- -- -- -- -- 600 50 -- -- -- -- -- -- -- -- -- -- -- 40 -- -- -- -- -- -- -- -- -- -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19/34 FEDS5424331-01 1 Semiconductor MSM5424331 Note: Measurement conditions Input pulse level Input timing reference level Output timing reference level Input rise/fall time Load condition : VIH = 2.1 V, VIL = 0.8 V : VIH = 2.1 V, VIL = 0.8 V : VOH = 2.2 V, VOL = 0.6 V : 2 ns : CL = 30 pF 20/34 -- tDFS 1 Semiconductor D/F -- t tWCLK DFH tWWCLL TIMING WAVEFORM -- tWAH tWADS tWXAS tWXAH tWXAH Valid A0 tWEDH tWES tSWE tIEDH tIES Valid A1 WCLK -- tWWCLH tWAS (FIFO Mode) Write Cycle (Address Setting Cycle) -- tWXAS tWXAH WADE/RX tWADH -- tWXAS Valid A8 tWXAH tWXAS -- WXAD -- Valid A9 LWE -- UWE -- -- IE -- -- Low WR/TR -- -- Low tDS tDH Valid tDS Valid tDH WXINC -- FEDS5424331-01 MSM5424331 DIN0 - 11 DIN12 - 23 -- -- 21/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Write Cycle (LWE/UWE Control) -- D/F -- -- WCLK -- -- WADE/RX -- -- IE -- -- WR/TR -- -- WXINC LWE UWE -- -- -- Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N) Valid D(N+1) Valid D(N+2) Low (N-2)CYCLE (N-1)CYCLE N CYCLE tWCLK (N+1) CYCLE (N+2) CYCLE Low High Low Low tWEH tWEDS tWEDH tWES -- DIN0 - 11 DIN12 - 23 -- Write Cycle (IE Control) -- D/F -- -- WCLK -- -- WADE/RX LWE UWE WR/TR -- -- WXINC -- -- IE -- Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N) Valid D(N+2) Valid D(N+3) Low (N-2)CYCLE (N-1)CYCLE N CYCLE tWCLK (N+2) CYCLE (N+3) CYCLE -- -- -- -- Low Low Low Low tIEH tIEDS tIEDH tIES -- DIN0 - 11 DIN12 - 23-- Note: In the IE = "L" cycle, the write address pointer is incremented, though no DIN data is written and the memory data is held. 22/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Write Cycle (Write Transfer) -- D/F -- -- WCLK -- -- WADE/RX -- -- WR/TR -- -- WXINC LWE UWE -- -- -- Valid D(N-3) Valid D(N-2) Valid D(N-1) Valid D(N) Low (N-2)CYCLE (N-1)CYCLE N CYCLE tWCLK Low tWTRS tWTDH tWTRH tWTDS Low tWEH tWEDS DIN0 - 11 -- DIN12 - 23-- Note: When finishing the write operation on a line, be sure to perform a write transfer operation because the write data on the line is stored in the memory cell. 23/34 -- tDFS 1 Semiconductor D/F -- tDFH tRCLK tWRCLL -- tRAH tRADS RCLK (FIFO Mode) Read Cycle (Address Setting Cycle) -- tWRCLH RADE/RX tRXAS tRXAH tRXAH tRXAH Valid B1 tREDH tSRE Valid B0 tRES tRXAS tRXAS -- tRAS tRADH -- tRXAS Valid B8 tRXAH -- RXAD -- Valid B9 RE -- -- -- Low RR -- -- Low tAC High-Z Valid Valid FEDS5424331-01 tOH RXINC -- -- DO0 - 23 -- MSM5424331 24/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Read Cycle (RE Control) -- D/F -- -- RCLK -- -- RADE/RX -- -- RR -- -- RXINC RE -- -- -- -- -- tOH Valid D(N-3) Valid D(N-2) Valid D(N-1) Low (N-2)CYCLE (N-1)CYCLE N CYCLE tRCLK (N+1) CYCLE (N+2) CYCLE Low Low Low tREH tREDS tDDRE Valid D(N) tREDH tRES tAC High-Z Valid D(N+1) Valid D(N+2) DO0 - 23 Note: In the cycle of RE = "H", the read address pointer is not incremented and the output enters the high impedance state. 25/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Write Reset Mode -- D/F -- -- WCLK -- -- WADE/RX -- -- WR/TR -- -- WXINC LWE UWE -- -- -- tSWE tDS Valid tDH tDS Valid tDH Low tWEDH tWES tDFS tDFH tWCLK tWWCLL tWWCLH tWRXDH tWRXS tWRXH tWRXDS tWRDH tWRS tWRH t WRDS DIN0 - 11 -- DIN12 - 23-- Note: Both the line address and word address are set to 0. Write Line Increment Mode -- D/F -- -- WCLK -- -- WADE/RX -- -- WR/TR -- -- WXINC LWE UWE -- -- -- tSWE tDS Valid tDH tDS Valid tDH tWRDH tWRS tWINDH tWINS tWRH t WRDS tWINH tDFH tWCLK tWWCLL tWWCLH tDFS tWINDS tWEDH tWES DIN0 - 11 -- DIN12 - 23-- Note: The line address is incremented by 1 and the word address is set to 0. 26/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Write Address Jump Mode -- D/F -- -- WCLK -- -- WADE/RX -- -- WR/TR -- -- WXINC LWE UWE -- -- -- tSWE tDS Valid tDH tDS Valid tDH tDFH tWCLK tWWCLL tWWCLH tWRXDH tWRXS tWRXH tWRXDS tWRDH tWRS tWINDH tWINS tWRH t WRDS tWINH t WINDS tWEDH tDFS tWES DIN0 - 11 -- DIN12 - 23-- Note: The line address is reset to the initialized addresses and the word address is set to 0. 27/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Read Line Hold Mode -- D/F -- -- RCLK -- -- RADE/RX -- -- RR -- -- RXINC RE -- -- -- -- DO0 - 23 -- High-Z tSRE tAC Valid tOH Valid Low tREDH tRES tRRDH Low tRRS tRRH tRRDS tDFH tRCLK tWRCLL tWRCLH tDFS Note: The line address is held and the word address is set to 0. Read Reset Mode -- D/F -- -- RCLK -- -- RADE/RX -- -- RR -- -- RXINC RE -- -- -- -- DO0 - 23 -- High-Z tSRE tAC Valid tOH Valid Low tREDH tRES tDFH tRCLK tWRCLL tWRCLH tRRXDH tRRXS tRRDH tRRS tRRXH t RRXDS tRRH t RRDS tDFS Note: Both the line address and word address are set to 0. 28/34 FEDS5424331-01 1 Semiconductor MSM5424331 (FIFO Mode) Read Line Increment Mode -- D/F -- -- RCLK -- -- RADE/RX -- -- RR -- -- RXINC -- RE -- -- -- DO0 - 23 -- High-Z Valid Valid tSRE tAC tOH tREDH tRES tRRDH Low tRRS tRRH t RRDS tRINH t RINDS tDFH tRCLK tWRCLL tWRCLH tDFS tRINDH tRINS Note: The line address is incremented by 1 and the word address is set to 0. Read Address Jump Mode -- D/F -- -- RCLK -- -- RADE/RX -- -- RR -- -- RXINC RE -- -- -- -- DO0 - 23 -- High-Z tSRE tAC Valid tOH Valid tRINDH tRINS tRINH t RINDS tREDH tRES tDFH tRCLK tWRCLL tWRCLH tRRXDH tRRXS tRRXH tRRXDS tRRDH tRRS tRRH t RRDS tDFS Note: The line address is reset to the initialized addresses and the word address is set to 0. 29/34 D/F (Block Access Mode) Write Cycle 1 Semiconductor WAIT tBWH tRPW tDRP tBS RAS tCASB tBC tCP tCAS tRSH tDCP tCRP tRCD CAS tASR Column tAHR t tASC AHC Row Address Row tWCS tWCH tCWCH tWCS LWE tCWCS UWE tFBDH tBDS Data-In n+1 Data-In n+2 Data-In n+3 Data-In n+4 Data-In n tBDS tBDH t tBDH t tBDH tBDS tBDH tBDS tBDH t tBDH tBDS BDS BDS BDS Data-In n+5 Data-In n+6 tBDH Data-In n+7 DQ0 - 11 Open Open Note: Data is written to L-BANK if LWE = "L" during a falling edge of RAS or is written to U-BANK if UWE = "L". A data write to L-BANK or to U-BANK is undefined if LWE and UWE = "L". FEDS5424331-01 MSM5424331 30/34 D/F (Block Access Mode) Read Cycle 1 Semiconductor WAIT tBRH tRPR tDRP tBS RAS tCASB tRSH tBC tCP tCAS tDCP tCRP tRCD CAS tASR Column tAHR tASC tAHC Row Address Row tRCS tRCH tRCS LWE UWE tRAC tBAC tBAC tBOH Data-Out n+1 tOFF tBAC tBOH Data-Out n+2 RE tDERE tBOH Data-Out n tBAC tBOH Data-Out n+3 tBAC tBOH Data-Out n+4 tBAC tBOH Data-Out n+5 tBAC tBOH Data-Out n+6 tDDRE Data-Out n+7 DQ0 - 11 Open Open FEDS5424331-01 MSM5424331 Note: Read data is read from L-BANK if A9 of the Row address is "0" and is read from U-BANK if A9 of the Row address is "1". 31/34 FEDS5424331-01 1 Semiconductor MSM5424331 (Block Access Mode) CAS before RAS Refresh Cycle D/F High WAIT tRC tRP RAS tRPC tCPN CAS tCSR tCHR tRASB tRP High RE tOFF DQ0 - 11 Open 32/34 FEDS5424331-01 1 Semiconductor MSM5424331 PACKAGE DIMENSIONS (Unit: mm) TSOP(2)70-P-400-0.50-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.49 TYP. 2/Nov. 13, 1998 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 33/34 FEDS5424331-01 1 Semiconductor MSM5424331 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 34/34 |
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